PMC-FPGA03F Virtex-II Pro PMC
FPGAモジュール / PMC/XMC
・User programmable Xilinx XC2VP50 Virtex-II Pro FPGA ・2 or 4x Fiber-optic Transceivers (front panel) ・Up to 3.125Gbps per transceiver ・64-bit user programmable data port (PMC user I/O P14) ・2x banks DDR SDRAM (64Mbytes per bank) ・3x banks QDR-II SRAM (up to 8Mx18-bit per bank) ・4Mbytes Flash Memory
AMC513
FPGAモジュール / AdvancedMC
・AMC FPGA carrier for FPGA Mezzanine Card (FMC) per VITA-57 ・AMC Ports 2-3 and 4-11 are routed to FPGA (protocols such as PCIe, SRIO, XAUI, etc. are FPGA programmable) ・Xilinx Virtex-6 FPGA in FF1759 package ・AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed ・On board PLL for buffering/multiplying and jitter cleaner ・Option for up to 2GB of DDR-I…
VPX3-450 3U VPX Virtex-5, 8640D
FPGAモジュール / OpenVPX
・3U VPX-REDI ・One Xilinx® Virtex®-5 Platform FPGA (LX155T, or SX95T) ・256 Mbytes DDR2 SDRAM attached to the FPGA, 2.2 GBytes/sec peak bandwidth ・18 Mbytes QDR-II+ SRAM attached to the FPGA in two banks, 4.4 GBytes/sec peak bandwidth per FPGA ・1 GHz 8640D dual-core processor with 1 Gbytes of DDR2 SDRAM in two banks ・XMC mezzanine site ・On-board PCI …
XMCV5
FPGAモジュール / PMC/XMC
・Xilinx Virtex-5 FPGA: FX100T with PPC440 hard cores, SX95T or LX110T ・External Memory: QDR2 SRAM, DDR2 SDRAM and SPI Flash ・Rear I/O - VITA 42.3 PCIe gen2 (to 5 GHz) or VITA 42.2 sRIO build option - Rocket I/O to 6.5 GHz via GTX ports - LVDS, GPIO, GbE, Serial ports ・Front I/O: GbE, Serial, LVDS, GPIO ・XMCV5V - EDK and ISE project with tested …
AMC516
FPGAモジュール / AdvancedMC
・AMC FPGA carrier for FPGA Mezzanine Card (FMC) per VITA-57 ・Xilinx Virtex-7 690T FPGA in FFG-1761 package ・AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (protocols such as PCIe, SRIO, XAUI, etc. are FPGA programmable) ・AMC Ports 12-15 and 17-20 are routed to the FPGA
VPX3-450 3U VPX Virtex-5, 8640D
FPGAモジュール / OpenVPX
・3U VPX-REDI ・One Xilinx® Virtex®-5 Platform FPGA (LX155T, or SX95T) ・256 Mbytes DDR2 SDRAM attached to the FPGA, 2.2 GBytes/sec peak bandwidth ・18 Mbytes QDR-II+ SRAM attached to the FPGA in two banks, 4.4 GBytes/sec peak bandwidth per FPGA ・1 GHz 8640D dual-core processor with 1 Gbytes of DDR2 SDRAM in two banks ・XMC mezzanine site ・On-board PCI …
FMC106
FPGAモジュール / FMC
・FPGA Mezzanine Card (FMC) per VITA-57 ・Single width ・Dual 1GbE/10GbE via SFP+ ・XAUI interface to the FMC ・RoHS compliant
CHAMP-WB 6U OpenVPX Virtex-7
FPGAモジュール / OpenVPX
・OpenVPX™ (VITA 65) profile MOD6-PAY-4F1Q2U2T-12.2.1-11, VPX REDI (VITA 48 option) ・Single user-programmable Xilinx Virtex-7 FPGAs (X690T or X980T), with ・8 GB DDR3L SDRAM in two banks ・Four 4-lane serial data plane links to the backplane (support up to 10.3 Gbps data rates) ・Gen2 SRIO or alternate fabrics with different FPGA cores ・One 4-…
AMC510
FPGAモジュール / AdvancedMC
・AMC FPGA carrier to add customize mezzanines modules ・Clock in/out ・Trig in/out ・Sync in/out ・AMC Ports 0-1 and 4-11 are routed to FPGA (protocols such as PCIe, SRIO, XAUI, etc. are FPGA programmable) ・Xilinx Virtex-5 FPGA in FF1136 package ・AMC FCLK, CLKA, CLKB, CLKC and CLKD are routed ・On board PLL for buffering/multiplying and jitter cleaner ・…
CHAMP-FX3 (VPX6-472) 6U OpenVPX Virtex-6
FPGAモジュール / OpenVPX
・6U OpenVPX (VITA 65) ・Dual user-programmable Xilinx Virtex-6 FPGAs (SX475T or LX550T), each with: ・2 GB DDR3 SDRAM in two banks ・Supports migration to 4 GB per FPGA ・72 MB QDRII+ SRAM in four banks ・Freescale Power Architecture MPC8640D processor ・Running at 1 GHz ・1 GB SDRAM in two banks ・Two Mezzanine sites with support for FMC (VITA …