FMC228 – FMC Quad ADC 12-bit @ 1 GSPS
FPGAモジュール / FMC
・FPGA Mezzanine Card (FMC) per VITA 57 ・Dual AD9234 ・Optional decimate-by-2 DDC per channel ・JESD204B ・2 GHz analog input full power bandwidth ・Option for Direct RF sampling clock via front panel ・On board wide-band PLL ・Trig In/Out ・RoHS compliant
AMC540 – Xilinx Virtex-7 FPGA AMC with Dual DSP
FPGAモジュール / AdvancedMC
・Xilinx Virtex-7 XC7VX690T FPGA ・DDR-3 Memory (3 banks of 64-bit, 6 GB Total) ・Dual DSP (optionally TMS320C6670 or TMS320C6678) ・8 GB of DDR-3 per CPU with ECC ・24 TX/RX Fibre via MTP/MPO Connector ・PCIe (AMC.1) and SRIO (AMC.4) on ports 4-7 and 8-11 per FPGA load ・GbE on ports 0,1 (AMC.2) ・Ports 12-15 and 17-20 routed to FPGA ・Layer two managed sw…
AMC592 – AMC FPGA Carrier for FMC, UltraSCALE
FPGAモジュール / FMC
・Carrier for FPGA Mezzanine Card (FMC) ・Single module, mid-size AMC ・Xilinx UltraSCALE XCKU115 FPGA ・AMC Ports 4-11 are routed to FPGA ・AMC Ports 12-15 and 17-20 are routed to the FPGA for direct FPGA to FPGA board communication ・AMC FCLKA, TCLKA, TCLKB, TCLKC and TCLKD are routed ・Clock jitter cleaner ・Two banks of 64-bit wide and a single bank of…
VPX519 – FPGA Carrier for FMC, 3U VPX, Artix-7
FPGAモジュール / FMC
・3U FPGA carrier for FPGA Mezzanine Card (FMC) per VITA-46 and VITA-57 ・Xilinx Artix-7 FPGA in FBG-676 package ・High-performance clock jitter cleaner ・VHDL reference design with source code ・Protocols such as PCIe and GbE are FPGA programmable ・Compatible with VadaTech and 3rd-party FMCs
MRT523 – MicroTCA.4 RTM for AMC523, 12 Ch ADC 16-bit @ 125 MSPS
FPGAモジュール / AdvancedMC
・MicroTCA.4 RTM for the AMC523 ・Double module, mid-size (full-size optional) ・Twelve channel ADC 16-bit @ 125 MSPS utilizing AD9653 device routed to AMC523 ・Two analog outputs from AMC523’s DAC Mezzanine ・ADC and DAC signals routed through a mezzanine
XMC-442 – Virtex-5 XMC
FPGAモジュール / PMC/XMC
・One user-programmable Xilinx® Virtex-5 FPGA Node (SX50T or SX95T) with: ・One bank of DDR2 SDRAM per FPGA node (256 MB total), up to 2.2 GBytes/sec of bidirectional bandwidth ・Two banks of QDR-II+ SRAM per FPGA node (18 MB total), up to 4.4 GBytes/sec of bidirectional bandwidth ・Three high-speed serial ports with up to 7.5 GBytes/sec of bi-directio…