・Low Voltage Differential Signaling (LVDS) - PMC Front Panel Mezzanine Module
・134 I/O lines routed as 64 differential pairs
・152-pin front panel connector
・Mixed voltage signalling
・FPGA Firmware blocks supplied in VHDL for integration into user applications
・Windows, VxWorks and Linux host PMC support
・134 I/O lines routed as 64 differential pairs
・152-pin front panel connector
・Mixed voltage signalling
・FPGA Firmware blocks supplied in VHDL for integration into user applications
・Windows, VxWorks and Linux host PMC support