600 Mbytes per second I/O transfer rate via the front panel connector (LVDS transceivers).
400 Mbytes per second PCI burst transfer rate over 300 Mbs sustained
Upgrade in future to 600 MBps sustained
Can interface to a wide variety of external high-speed devices.
"Deep FIFO buffers" (4 Megabytes) allow data bursts to be transferred over the PCI bus.
64-Bit data transfers on the PCI bus.
On-board cable controller, FIFOs, and DMA engine provide for continuous data transfer.
Data input/output clock rate up to 150 MHz.
64-Bit, 66 MHz PCI v2.2 compliant
Cable data input/output width of 32 bits.
8 bi-directional signals can be used as clocks and/or handshaking protocol.
400 Mbytes per second PCI burst transfer rate over 300 Mbs sustained
Upgrade in future to 600 MBps sustained
Can interface to a wide variety of external high-speed devices.
"Deep FIFO buffers" (4 Megabytes) allow data bursts to be transferred over the PCI bus.
64-Bit data transfers on the PCI bus.
On-board cable controller, FIFOs, and DMA engine provide for continuous data transfer.
Data input/output clock rate up to 150 MHz.
64-Bit, 66 MHz PCI v2.2 compliant
Cable data input/output width of 32 bits.
8 bi-directional signals can be used as clocks and/or handshaking protocol.
