・FPGA Mezzanine Card (FMC) per VITA 57
・TI ADC12J4000 ADC
・Usable output bandwidth of 800 MHz at 4x decimation and 4000 MSPS
・Usable output bandwidth of 100 MHz at 32x decimation and 4000 MSPS
・Bypass Mode for full Nyquist output bandwidth
・Analog Devices AD9129 DAC
・DC-to-1.4 GHz in Baseb and mode
・DC-to-1.0 GHz in 2x Interpolation mode
・1.4 to 4.2 GHz in Mix-Mode
・Excellent dynamic performance
・Front panel interface includes CLK In, Trig In, AnalogIn/Out, and GPIO
・Ultra Low-Noise wide-band PLL
・Option to route high speed sampling clock via the front panel for the ADC and the DAC
・On-chip delay locked loops (DLLs) optimize timing between different clock domains.
・RoHS compliant
・TI ADC12J4000 ADC
・Usable output bandwidth of 800 MHz at 4x decimation and 4000 MSPS
・Usable output bandwidth of 100 MHz at 32x decimation and 4000 MSPS
・Bypass Mode for full Nyquist output bandwidth
・Analog Devices AD9129 DAC
・DC-to-1.4 GHz in Baseb and mode
・DC-to-1.0 GHz in 2x Interpolation mode
・1.4 to 4.2 GHz in Mix-Mode
・Excellent dynamic performance
・Front panel interface includes CLK In, Trig In, AnalogIn/Out, and GPIO
・Ultra Low-Noise wide-band PLL
・Option to route high speed sampling clock via the front panel for the ADC and the DAC
・On-chip delay locked loops (DLLs) optimize timing between different clock domains.
・RoHS compliant
