・ADC AD9625
・8 JESD204B lanes from the ADC isrouted to the FMC
・12-bit at 2.6 GSPS
・Wide full power bandwidth supports IF sampling of signals up to 2 GHz
・DAC AD9129
・14-bit at 5.6 GSPS
・FPGA Mezzanine Card (FMC) per VITA 57
・Excellent dynamic performance
・Front panel interface includes CLK In, Trig Inand Trig Out
・8 JESD204B lanes from the ADC isrouted to the FMC
・12-bit at 2.6 GSPS
・Wide full power bandwidth supports IF sampling of signals up to 2 GHz
・DAC AD9129
・14-bit at 5.6 GSPS
・FPGA Mezzanine Card (FMC) per VITA 57
・Excellent dynamic performance
・Front panel interface includes CLK In, Trig Inand Trig Out
