・FPGA Mezzanine Card (FMC) per VITA 57
・TI ADC12J4000 ADC
・E2V EV12DS400 DAC
・Excellent dynamic performance
・Front panel interface includes CLK In, Trig In, AnalogIn/Out, and GPIO
・Ultra Low-Noise wide-band PLL
・On-chip delay locked loops (DLLs) optimize timing between different clock domains.
・TI ADC12J4000 ADC
・E2V EV12DS400 DAC
・Excellent dynamic performance
・Front panel interface includes CLK In, Trig In, AnalogIn/Out, and GPIO
・Ultra Low-Noise wide-band PLL
・On-chip delay locked loops (DLLs) optimize timing between different clock domains.
