・FPGA Mezzanine Card (FMC) per VITA 57
・Utilizes Analog Devices AD9361 transceiver
・Dual complete transceiver signal chain solution
・Frequency range 70 MHz to 6 GHz
・Instantaneous bandwidth from 200 kHz to 56 MHz
・Multiplexed 2x RF inputs on each RF channel
・Time Domain Duplex (TDD) and Frequency Domain Duplex (FDD) compatible
・On-board clocking or external clock with multi-card synchronization capability
・Low Pin Count (LPC) 160-pin connector
・RoHS compliant
・Utilizes Analog Devices AD9361 transceiver
・Dual complete transceiver signal chain solution
・Frequency range 70 MHz to 6 GHz
・Instantaneous bandwidth from 200 kHz to 56 MHz
・Multiplexed 2x RF inputs on each RF channel
・Time Domain Duplex (TDD) and Frequency Domain Duplex (FDD) compatible
・On-board clocking or external clock with multi-card synchronization capability
・Low Pin Count (LPC) 160-pin connector
・RoHS compliant