・Analog Input:
・Number of Channels: 4, single-ended
・Sampling Frequency: Up to 250MSPS
・Full Scale Input Voltage: 18.8 dBm
・Device: 4x Intersil ISLA216P25
・Input Bandwidth (3dB): up to 500 MHz
・SFDR (at 105 MHz): 84 dBFS (typ)
・SNR (at 105 MHz): 70 dBFS (typ)
・ENOB (at 105 MHz): 11.3 bits (typ)
・Input Impedance: 50 Ohm, AC coupled
・Input Connector: Front panel MMCX
・Sample Clock:
・Connector: Front panel MMCX
・Input impedance: 50 Ohm, AC coupled LVPECL
・Clock Input: 40-250 MHz (RF) or 10 MHz reference input
・Internal clock selectable from:
・SiLabs Si571 programmable clock (frequency range 40 - 250 MHz)
・Programmable clock source (10MHz - internal or external)
・Configure by FPGA
・Software/HDL Code:
・FusionXF software/HDL tools for Xilinx Virtex-5/6 hosts
・Environmental:
・Ruggedization levels: Air-cooled level 0 and level 100, conduction-cooled level 200
・Number of Channels: 4, single-ended
・Sampling Frequency: Up to 250MSPS
・Full Scale Input Voltage: 18.8 dBm
・Device: 4x Intersil ISLA216P25
・Input Bandwidth (3dB): up to 500 MHz
・SFDR (at 105 MHz): 84 dBFS (typ)
・SNR (at 105 MHz): 70 dBFS (typ)
・ENOB (at 105 MHz): 11.3 bits (typ)
・Input Impedance: 50 Ohm, AC coupled
・Input Connector: Front panel MMCX
・Sample Clock:
・Connector: Front panel MMCX
・Input impedance: 50 Ohm, AC coupled LVPECL
・Clock Input: 40-250 MHz (RF) or 10 MHz reference input
・Internal clock selectable from:
・SiLabs Si571 programmable clock (frequency range 40 - 250 MHz)
・Programmable clock source (10MHz - internal or external)
・Configure by FPGA
・Software/HDL Code:
・FusionXF software/HDL tools for Xilinx Virtex-5/6 hosts
・Environmental:
・Ruggedization levels: Air-cooled level 0 and level 100, conduction-cooled level 200
