・OpenVPX™ (VITA 65) profile MOD6-PAY- 4F1Q2U2T-12.2.1-11, VPX REDI (VITA 48 option)
・Three user-programmable Xilinx Virtex-7 FPGAs (585T or X690T), each with:
・4 GB DDR3L SDRAM in two 64-bit banks
・36 MB QDRII+ SRAM in two 36-bit banks
・Three or Four 10.3 GHz 4-lane high-speed serial links to the backplane
・Eight or twenty LVDS pairs to the backplane
・Two FMC interfaces with 80 differential signal pairs
・Onboard PCIe Gen3 switch
・Onboard SRIO Gen2 switch
・Xilinx ZYNQ FPGA with Dual ARM Cortex A9 processor
・1 GB DDR3L SDRAM
・256 MB application flash
・Multi-board synchronous clock
・FXTools BSP and FPGA design kit with highly-optimized IP Blocks, development environment, reference designs, scriptable simulation test benches and software libraries VxWorks® and Linux® variants available
・Continuum IPC – inter-processor communications middleware available
・Backplane I2C/IPMI control for power on/off card and sensor information
・VITA 48 1” pitch format
・Ruggedization levels
・Level 0 (Commercial)
・Air-cooled level 100
・Conduction-cooled level 200
・Three user-programmable Xilinx Virtex-7 FPGAs (585T or X690T), each with:
・4 GB DDR3L SDRAM in two 64-bit banks
・36 MB QDRII+ SRAM in two 36-bit banks
・Three or Four 10.3 GHz 4-lane high-speed serial links to the backplane
・Eight or twenty LVDS pairs to the backplane
・Two FMC interfaces with 80 differential signal pairs
・Onboard PCIe Gen3 switch
・Onboard SRIO Gen2 switch
・Xilinx ZYNQ FPGA with Dual ARM Cortex A9 processor
・1 GB DDR3L SDRAM
・256 MB application flash
・Multi-board synchronous clock
・FXTools BSP and FPGA design kit with highly-optimized IP Blocks, development environment, reference designs, scriptable simulation test benches and software libraries VxWorks® and Linux® variants available
・Continuum IPC – inter-processor communications middleware available
・Backplane I2C/IPMI control for power on/off card and sensor information
・VITA 48 1” pitch format
・Ruggedization levels
・Level 0 (Commercial)
・Air-cooled level 100
・Conduction-cooled level 200
