・Dual ADC AD9625, 12-Bit @ 2.6 GSPS in single module, mid-size (full-size optional)
・Xilinx Virtex-7 690T FPGA in FFG-1761 package
・Quad banks of QDR-II+ memory, 576 Mb total (36-bit wide)
・Single DDR3 1Gb (16-bit wide)
・AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (protocols such as PCIe, SRIO, XAUI, etc. are FPGA programmable)
・AMC Ports 12-15 and 17-20 are routed to the FPGA
・Xilinx Virtex-7 690T FPGA in FFG-1761 package
・Quad banks of QDR-II+ memory, 576 Mb total (36-bit wide)
・Single DDR3 1Gb (16-bit wide)
・AMC Ports 4-11 are routed to FPGA per AMC.1, AMC.2 and AMC.4 (protocols such as PCIe, SRIO, XAUI, etc. are FPGA programmable)
・AMC Ports 12-15 and 17-20 are routed to the FPGA
