Two Wideband 16-Bit 40 MSPS Analog Output Channels
Clocking Rates from Zero to 40 MSPS per Channel; Aggregate Rates to 80 MSPS
Software-Selectable Output Ranges: ±3V, ±1.5V, ±0.75V Optional ±10V, ±5V, ±2.5V ranges available, with reduced throughput and loading.
1-MByte FIFO Data Buffer; 512-Ksample Capacity, with DMA Support
66MHz PCI Compatibility and Local Data Packing provide Maximum Throughput
Dynamic Linearity Correction: 0.003% DNL; 0.005% INL
Output Clocking from Internal Rate Generator or External Source
Simultaneous or Independent Output Clocking
Dynamic control of Clocking Rates with Embedded Function Codes
Hardware Clock and Sync I/O for Multiboard Synchronization
16-Bit 300-KSPS Analog Input Channel
Byte-Wide Digital I/O Port
Dual Rate Generators and Dual 24-Bit Timers
On-Demand Internal Autocalibration ensures Maximum Accuracy under All Conditions
Conforms to PCI Local Bus
Specification, Revision 2.3, with Universal Signaling
Clocking Rates from Zero to 40 MSPS per Channel; Aggregate Rates to 80 MSPS
Software-Selectable Output Ranges: ±3V, ±1.5V, ±0.75V Optional ±10V, ±5V, ±2.5V ranges available, with reduced throughput and loading.
1-MByte FIFO Data Buffer; 512-Ksample Capacity, with DMA Support
66MHz PCI Compatibility and Local Data Packing provide Maximum Throughput
Dynamic Linearity Correction: 0.003% DNL; 0.005% INL
Output Clocking from Internal Rate Generator or External Source
Simultaneous or Independent Output Clocking
Dynamic control of Clocking Rates with Embedded Function Codes
Hardware Clock and Sync I/O for Multiboard Synchronization
16-Bit 300-KSPS Analog Input Channel
Byte-Wide Digital I/O Port
Dual Rate Generators and Dual 24-Bit Timers
On-Demand Internal Autocalibration ensures Maximum Accuracy under All Conditions
Conforms to PCI Local Bus
Specification, Revision 2.3, with Universal Signaling
