Six Differential Analog Inputs with dedicated 18-Bit ADC per channel
True Simultaneous Sampling of all inputs from Zero to 12MSPS per channel
2.0 Megasample input data FIFO buffer
SAR Architecture; No minimum sample rate; Minimum Latency
Selectable Input Ranges: (Order Wideband or High-Level)
Wideband: ±2.5V, ±1.25V, ±0.625V ; or High-Level: ±10V, ±5V, ±2.5V
Miniature MMCX coaxial system connectors for analog inputs and timing I/O.
Hardware Clock and Sync I/O for multiboard operation
Timing Controlled by internal rate generators, by software clocking, or externally
DMA Engine minimizes bus congestion
Dual Power Conversion for optimum internal power voltage integrity
Internal on-demand Autocalibration of all channels
PCI Express control interface
XMC form factor
Extended-temperature version available
True Simultaneous Sampling of all inputs from Zero to 12MSPS per channel
2.0 Megasample input data FIFO buffer
SAR Architecture; No minimum sample rate; Minimum Latency
Selectable Input Ranges: (Order Wideband or High-Level)
Wideband: ±2.5V, ±1.25V, ±0.625V ; or High-Level: ±10V, ±5V, ±2.5V
Miniature MMCX coaxial system connectors for analog inputs and timing I/O.
Hardware Clock and Sync I/O for multiboard operation
Timing Controlled by internal rate generators, by software clocking, or externally
DMA Engine minimizes bus congestion
Dual Power Conversion for optimum internal power voltage integrity
Internal on-demand Autocalibration of all channels
PCI Express control interface
XMC form factor
Extended-temperature version available