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8 Differential 24-Bit Analog Input Channels
Delta-Sigma Converter per Channel, with Linear Phase Digital Antialias Filtering
Sample rates from 2 KSPS to 200 KSPS per Channel
Software-Selectable Input Ranges: ±2.5V, ±5V, ±10V
256 K-sample FIFO Buffer
Synchronous or Independent ADC Clocking
Internal Sample Rate Generators
Hardware Sync and Clock I/O for Multiboard Synchronization
Supports GPS Synchronization to a 1PPS Input
Low Phase Skew; Typically Less than 55ns with Fsig < 0.35*Fsamｐ
DMA Engine Supports both Block-Mode and Demand-Mode Transfers
Low Power Consumption. 6 Watts Typical. Only +5VDC Required from PCI bus.
100dB Dynamic Range to 100KSPS; 93 dB SINAD
On-demand Autocalibration Ensures DC Precision as well as AC performance
Integrated DC/DC Conversion and Regulation of Precision Internal Supply Voltages
Conforms to PCl Bus Specification, Revision 2.3, with Universal Signaling
Triggered Acquisition feature supports external acquisition triggering
Delta-Sigma Converter per Channel, with Linear Phase Digital Antialias Filtering
Sample rates from 2 KSPS to 200 KSPS per Channel
Software-Selectable Input Ranges: ±2.5V, ±5V, ±10V
256 K-sample FIFO Buffer
Synchronous or Independent ADC Clocking
Internal Sample Rate Generators
Hardware Sync and Clock I/O for Multiboard Synchronization
Supports GPS Synchronization to a 1PPS Input
Low Phase Skew; Typically Less than 55ns with Fsig < 0.35*Fsamｐ
DMA Engine Supports both Block-Mode and Demand-Mode Transfers
Low Power Consumption. 6 Watts Typical. Only +5VDC Required from PCI bus.
100dB Dynamic Range to 100KSPS; 93 dB SINAD
On-demand Autocalibration Ensures DC Precision as well as AC performance
Integrated DC/DC Conversion and Regulation of Precision Internal Supply Voltages
Conforms to PCl Bus Specification, Revision 2.3, with Universal Signaling
Triggered Acquisition feature supports external acquisition triggering
