・ADC ADC12DJ3200
・Option for ADC12DJ270 or ADC12DJ1600
・8 JESD204B lanes from the ADC is routed to the FMC
・12-bit at 6.4 GSPS
・Wide full power bandwidth supports IF sampling of signals up to 6 GHz
・DAC AD9164/AD9162
・16-bit at 12 GSPS
・FPGA Mezzanine Card (FMC) per VITA 57
・Excellent dynamic performance
・Front panel interface includes CLK In, Trig In and Trig Out
・Option for ADC12DJ270 or ADC12DJ1600
・8 JESD204B lanes from the ADC is routed to the FMC
・12-bit at 6.4 GSPS
・Wide full power bandwidth supports IF sampling of signals up to 6 GHz
・DAC AD9164/AD9162
・16-bit at 12 GSPS
・FPGA Mezzanine Card (FMC) per VITA 57
・Excellent dynamic performance
・Front panel interface includes CLK In, Trig In and Trig Out
