・FPGA Mezzanine Card (FMC) per VITA 57
・Dual Texas Instruments ADC12J4000 ADC
・Four JESD204B lanes per ADC are routed to the FMC connector
・Usable output bandwidth of 800 MHz at 4x decimation and 4000 MSPS
・Usable output bandwidth of 100 MHz at 32x decimation and 4000 MSPS
・Excellent dynamic performance
・Front panel interface includes CLK In, Trig In, Analog In, and GPIO
・Ultra Low-Noise wide-band PLL
・RoHS compliant
・Dual Texas Instruments ADC12J4000 ADC
・Four JESD204B lanes per ADC are routed to the FMC connector
・Usable output bandwidth of 800 MHz at 4x decimation and 4000 MSPS
・Usable output bandwidth of 100 MHz at 32x decimation and 4000 MSPS
・Excellent dynamic performance
・Front panel interface includes CLK In, Trig In, Analog In, and GPIO
・Ultra Low-Noise wide-band PLL
・RoHS compliant
