・FPGA Mezzanine Card (FMC) per VITA-57
・Single module
・Dual ADC with EV12AS200AZP
・12-bit 1.5GSPS
・Full power input Bandwidth at 1.5GSPS is 2.3GHz
・Very low latency < 5Clock Cycles
・Dual DAC with TI DAC39J82
・16-bit 2.8GSPS
・JESD204B 8 lanes
・On board wide-band PLL
・RF clock input reference
・Trig In/Out
・RoHS compliant
・Single module
・Dual ADC with EV12AS200AZP
・12-bit 1.5GSPS
・Full power input Bandwidth at 1.5GSPS is 2.3GHz
・Very low latency < 5Clock Cycles
・Dual DAC with TI DAC39J82
・16-bit 2.8GSPS
・JESD204B 8 lanes
・On board wide-band PLL
・RF clock input reference
・Trig In/Out
・RoHS compliant