・FPGA Mezzanine Card (FMC) per VITA-57
・ADC EV10AS150B @ 2.6 GSPS
・5 GHz Full Power Input Bandwidth (–3dB)
・True single core architecture (no calibration required)
・Full scale Analog input Voltage Span 500 mVpp
・Ultra Low Jitter wideband PLL Synthesizer
・Option for Direct RF clock sampling or reference clock input
・The ADC RF input can be differential or single ended
・ADC EV10AS150B @ 2.6 GSPS
・5 GHz Full Power Input Bandwidth (–3dB)
・True single core architecture (no calibration required)
・Full scale Analog input Voltage Span 500 mVpp
・Ultra Low Jitter wideband PLL Synthesizer
・Option for Direct RF clock sampling or reference clock input
・The ADC RF input can be differential or single ended
