・User programmable Xilinx XC2VP50 Virtex-II Pro FPGA
・2 or 4x Fiber-optic Transceivers (front panel)
・Up to 3.125Gbps per transceiver
・64-bit user programmable data port (PMC user I/O P14)
・2x banks DDR SDRAM (64Mbytes per bank)
・3x banks QDR-II SRAM (up to 8Mx18-bit per bank)
・4Mbytes Flash Memory
・2 or 4x Fiber-optic Transceivers (front panel)
・Up to 3.125Gbps per transceiver
・64-bit user programmable data port (PMC user I/O P14)
・2x banks DDR SDRAM (64Mbytes per bank)
・3x banks QDR-II SRAM (up to 8Mx18-bit per bank)
・4Mbytes Flash Memory
